Optimization circuitry and control for a synchronous memory device with programmable latency period
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 6, 1996
Grant Date -
N/A
app pub date -
Mar 13, 1995
filing date -
Mar 13, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method and apparatus for optimizing the speed path of a memory access operation in a synchronous depending upon the present latency period for the synchronous DRAM. The improved memory device compensates the time between row address latching and column address latching (tRCD) by delaying the presentment of the column address to compensate tRCD from the time available for column address latching to valid data-out (tAA) when tRCD is the critical parameter. Optimization circuitry reduces the amount of time available for tAA and 'shifts' it to the more critical parameter tRCD, enabling the optimization or reduction of the time allocated for tRCD by compensating tRCD with the extra time available for tAA. Thus, the memory access optimization circuitry enables an optimization or reduction in the total memory access time by compensating the optimized tRCD with the extra time available for tAA.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully