Fine resolution digital delay line with coarse and fine adjustment stages
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United States of America Patent
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Aug 6, 1996
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N/A
app pub date -
Oct 18, 1994
filing date -
Feb 17, 1993
priority date (Note) -
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Abstract
A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.
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