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Abstract

A debug port in accordance with the invention provides circuitry for enabling system (hardware and software) development within an inaccessible computer processor. In one embodiment, a debug port is incorporated within the internal logic of a single-chip, reduced instruction set signal processor referred to as the signal processor. A fully implemented debug port is comprised of five interacting functional elements: debug bus unit (DBU), debug command unit (DCU), debug instruction Unit (DIU), debug inject/extract unit (DJU), and a debug flow unit (DFU). The DBU provides circuitry for buffering data received from the signal processor and other functional elements within the debug port as well as accepting data from an external source. The DBU provides for off-chip connections. The DCU provides circuitry for decoding and executing debug commands received by the debug port. The DIU provides circuitry to insert one or more instructions with, or without, data into the instruction stream of the signal processor. The DJU provides circuitry for injecting external sources of information (e.g., an analog input signal, external control signals, or repetitious data signals) into the signal processor under program control. The DFU provides circuitry for monitoring program/task execution.

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First Claim