Non-volatile semiconductor memory device and memory system using the same

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United States of America Patent

PATENT NO 5546351
SERIAL NO

08326281

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Abstract

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The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBA1-1 SHIBAURA 1-CHOME MINATO-KU TOKYO 105-0023

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aritome, Seiichi Kawasaki, JP 291 8244
Asano, Masamichi Tokyo-To, JP 97 2317
Itoh, Yasuo Kawasaki, JP 72 2559
Iwata, Yoshihisa Yokohama, JP 192 4520
Kato, Hideo Kawasaki, JP 230 3406
Momodomi, Masaki Yokohama, JP 58 2245
Nakai, Hiroto Yokohama, JP 68 2617
Nakamura, Hiroshi Kawasaki, JP 877 11765
Odaira, Hideko Machida, JP 21 593
Okamoto, Yutaka Kawasaki, JP 117 1413
Shirota, Riichiro Fujisawa, JP 208 7211
Tanaka, Tomoharu Yokohama, JP 338 14532
Tanaka, Yoshiyuki Yokohama, JP 290 4679
Tokushige, Kaoru Yokohama, JP 37 1005

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