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Abstract

A packet switch (25.sub.1) contains input port circuits (310) and output port circuits (380) inter-connected through two parallel paths: a multi-slot central queue (350) and a low latency by-pass cross-point switching matrix (360). The central queue has one slot dedicated to each output port to store a message portion ('chunk') destined for only that output port with the remaining slots being shared for all the output ports and dynamically allocated thereamong, as the need arises. Only those chunks which are contending for the same output port are stored in the central queue; otherwise, these chunks are routed to the appropriate output ports through the cross-point switching matrix. Each receiver classifies its resident chunks (as critical or non-critical) based upon both the urgency with which that chunk must be transmitted to its destination output port and by the status of the central queue. A critical chunk, i.e. one that must be transported as soon as possible to an output port is stored within the dedicated slot for that particular output port. Non-critical chunks are stored within available shared slots in the central queue. Independent least recently used arbiters (368, 385) separately control read and write access to the central queue based upon requests for service issued by input and output port circuits in order to impart assure fair access by each of these ports.

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