Importance

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Abstract

An emulation modeling apparatus (54) comprises a combination of a device under simulation (48) to be emulated and means for keeping the device under simulation (48) in a quiescent state at normal operating speeds and in a normal operating sequence so as to allow dual access to the emulation modeling apparatus (54) without loss of data or accuracy of functions. One access is from a host simulation environment (26) while the other is from a model debug user interface (20) where internal architecturally visible registers and status are available to the user for greater debug control on the simulated subsystem within simulation environment (26). Specifically, any of a wide variety of physical VLSI circuits (48) to be modeled is kept in a quiescent state after power-on by a device control (50). It is then accessed through simulation means by simulated subsystem within a simulation environment (26), to change the architecturally visible internal state of the VLSI circuit (48). Control (50) brings VLSI circuit (48) out of the quiescent state and submits the requested simulated access. After taking the response, control (50) returns VLSI circuit (48) again to its quiescent state so as to keep its internal state current. The response is sent back to simulation environment (26) to update the simulated subsystem. Independently, any user request for accessing the architecturally visible internal state of the circuit is gathered by model debug and user interface (20). Interface (20) enables control (50) to bring VLSI circuit (48) out of the quiescent state and to submit the user request access. Subsequently, control (50) monitors the response and returns VLSI circuit (48) to its quiescent state so as to maintain the internal state of VLSI circuit (48) current. Control (50) then sends the response back to user interface (20). VLSI circuit (48) thus is always kept ready and current for the next request, either from simulation environment (26) or from user interface (20) without having to reset it. If any user defined breakpoint condition is met during the simulated accesses on the VLSI circuit (48), this information is forwarded by control (50) to simulation environment (26) for stopping the simulation and to user interface (20) to update the debug screen accordingly.

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First Claim