Importance

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Abstract

A burst mode static random access memory (SRAM) (10) is disclosed that includes an address transition detect signal (ATD) generating circuit (14) that provides either an asynchronous ATD signal (a-ATD) or a synchronous ATD signal (s-ATD) depending upon the logic state of a mode signal (ATM). A rising edge of the a-ATD signal is generated by a change in address. A falling edge is generated after a predetermined time period according an a-ATD circuit (60) within the ATD generating circuit (14). A falling edge of the s-ATD signal is generated by a rising edge of an internal synchronous clock pulse (CLAT). The rising edge of the s-ATD signal is generated when data are sensed on data lines (40) by an end-of-cycle circuit (20). If ATM is high, the a-ATD signal is used for timing on the SRAM (10). If ATM is low, timing is determined according to the s-ATD signal. An ATD control circuit (16) is provided to generate I/O control signals in response to the ATD signal (either s-ATD or a-ATD). On a rising edge of the ATD signal the I/O control signals place the SRAM (10) in a precharge/equalization state wherein I/O lines (24, 32, 40) are equalized and sensing circuits (28, 34) are disabled. On a falling edge of the ATD signal, the SRAM (10) is placed in a read/write mode wherein the I/O lines (24, 32, 40) are ready to sense read data or be driven by written data, and sensing circuits (28, 34) are enabled for a read operation, or alternatively disabled for a write operation.

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First Claim