Bit stack wiring channel optimization with fixed macro placement and variable pin placement
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United States of America Patent
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Aug 20, 1996
Grant Date -
N/A
app pub date -
Feb 10, 1995
filing date -
Feb 10, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Wiring channel assignment in very large scale integrated (VLSI) bit stack macros is optimized for fixed macro placement and variable pin placement. Nets are first prioritized by length with the longest nets having highest priority. Nets are then routed between the appropriate macros according to their priority. Pin rails or position are assigned dynamically, rather than being predetermined, as the nets are being placed with a preference towards the nearest edge of the macro, in order to minimize net length and maximize sharing of wiring channels among multiple nets.
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