Secondary clock source for low power, fast response clocking
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United States of America Patent
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Aug 27, 1996
Grant Date -
N/A
app pub date -
Sep 29, 1995
filing date -
Sep 29, 1995
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Abstract
An integrated digital logic circuit includes a free-running secondary clock oscillator for generating free-running clocking pulses and a frequency-stabilized master oscillator for generating primary clocking pulses. A clock signal selector selects and puts out either the secondary clocking pulses or the primary clocking pulses depending upon integrated circuit operations/applications. A method for rapidly generating clocking signals during an integrated circuit start-up interval is also described.
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