Multiphase clock synthesizer having a plurality of phase shifted inputs to a plurality of phase comparators in a phase locked loop
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United States of America Patent
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Aug 27, 1996
Grant Date -
N/A
app pub date -
Jan 27, 1995
filing date -
Jan 27, 1995
priority date (Note) -
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Abstract
A phase-locked loop wherein the output signal is effectively sampled at an increased rate from conventional phase-locked loops, allowing for a greater increase in the ratio of the output frequency to the input frequency while reducing the possibility of jitter or failure to lock. Multiple differently phased reference signals and correspondingly phased feedback signals are produced. The comparison of the feedback signals and the reference signals produce multiple error signals which are combined to adjust the oscillation frequency of the voltage-controlled oscillator.
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