Method and apparatus for designing integrated circuits according to master slice approach

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United States of America Patent

PATENT NO 5551014
SERIAL NO

08396789

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A CAD system designs mask patterns for use in a master slice integrated circuit processing. The system includes an input device such as a mouse interface, and a display unit for symbolically displaying circuit elements and cells. A first data base stores a net list of circuit design information. A second data base stores data relating to the structure of a master slice bulk and various types of elemental cells formed in the master slice. A processing unit of the CAD system causes the display unit to display both a circuit design scheme and the master slice bulk on a screen of the display unit. The processing unit produces data about the initial positions of a pair of contact hole patterns by which a resistor is defined in a resistive cell region of the master slice, and automatically shifts the contact hole patterns from the initial positions to another position, in order to avoid interference between a wiring pattern on the master slice bulk and the contact hole patterns.

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Patent Owner(s)

Patent OwnerAddress
FUJITSU LIMITED1-1 KAMIKODANAKA 4-CHOME NAKAHARA-KU KAWASAKI-SHI KANAGAWA 211-8588
FUJITSU VLSI LIMITED1884-2 KOZOJI-CHO 2-CHOME KASUGAI-SHI AICHI 487

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sato, Noriaki Kasugai, JP 118 870
Yoshida, Kazuhiro Kasugai, JP 333 2369

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