Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program
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United States of America Patent
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Aug 27, 1996
Issued Date -
N/A
app pub date -
Jun 4, 1992
filing date -
May 17, 1991
priority date (Note) -
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status (Latency Note)
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Abstract
A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. The system includes a first interrupt mask register having a bit for indicating whether an interrupt is to be recognized by the processor, a second interrupt mask register having a bit for indicating whether the interrupt is to be recognized by a further circuit, and an arrangement responsive to a load of the first mask register for conforming the bit of the second mask register to the bit of the first mask register in a manner invisible to an application program being executed by the processor.
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