Component video signal to composite video signal encoding system, control system and method
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United States of America Patent
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-
Sep 10, 1996
Issued Date -
N/A
app pub date -
Jan 5, 1993
filing date -
Oct 20, 1989
priority date (Note) -
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status (Latency Note)
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Abstract
In a component video signal to composite video signal encoding system (10), the component input signals are stored in a first in, first out (FIFO) memory. The FIFO memory is connected by 1 luminance and 2 chrominance outputs to a rate converter, which increases the digital sampling rate of the signals as received from the FIFO memory. The rate converter is in turn connected by 1 luminance and 2 chrominance outputs to luminance and chrominance processing circuits. The luminance and chrominance processing circuits produce the composite video signals, and are connected to a D2 standard driver circuit. The output of the D2 driver circuit is D2 standard digital component signals. The luminance and chrominance processing circuits are also connected to a digital to analog (D/A) converter. The output of the D/A converter is an analog PAL or NTSC component video signal.
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