Importance

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Abstract

A method applicable to a host computer system having a system bus connected to a CPU, and a PCMCIA controller having status registers, means for supplying back off signals to the CPU and line buffers capable of being in a normal and high impedance state. A multi pin connector is located in each card socket and connected to a line buffer. Each connector has common address, data and control pins, power pins, ground pins longer than the data pins and card detect signal pins shorter than the signal pins. The first step is to detect the commencement of an insertion or removal of a PCMCIA card to or from a socket by monitoring the ground and card detect signal pins. After detection, commence termination of all CPU usage of common address, data and control lines by asserting a back off signal. Next, determine if the usage is terminated by monitoring the status registers in the controller. Next, place the common address, data and control lines in a high impedance state. Next, detect that the PC card has been completely inserted or removed by monitoring the ground pins or the card detect signal pins. Next, apply power to the PCMCIA card socket. After a delay return the common address, data and control lines to their normal operating impedance level.

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First Claim