Importance

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Abstract

An improved cache memory architecture is disclosed, having particular application in a cache having static random access memory (RAM). In a typical static RAM memory utilized as a cache, the cache has the requirement that it must access many more bits than is required for selection. A single wordline of the RAM may span an entire memory array, and the activation of the entire wordline results in many more bitlines activated than will actually be selected by the Y decoder. As a result, power is wasted. The present invention provides a cache memory in which even and odd columns are segregated, wherein the even addressed columns may be placed in a first set (0) and the odd addressed columns in a second set (1). The wordline decode includes two wordlines per row rather than the typical single wordline in prior art systems. The first wordline corresponds to the 'even' wordline, and the second wordline corresponds to the 'odd' wordline (set 1). Only one wordline is activated at any time to save power. The wordline decoder of the present invention utilizes an address bit (for example, the low order bit) to select either the driver for the columns corresponding to the even wordline or to the odd wordline. Although the present invention requires additional drivers, only one driver is activated at any one time. It has been found that the architecture of the present invention provides a total power savings in a read operation approaching fifty percent.

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First Claim