Method of forming wirings for integrated circuits by electroplating
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United States of America Patent
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Sep 17, 1996
Grant Date -
N/A
app pub date -
Mar 27, 1995
filing date -
Mar 28, 1994
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A method for forming wirings of an integrated circuit comprises a step of forming wirings on a substrate, a step of coating the wirings with a thin under metal layer, a step of coating the under metal layer with a mask except a part of the under metal layer, a first etching step of removing the under metal layer which is not coated by the mask to expose upper portions of at least ones of the wirings, an electroplating step of depositing a plating metal layer on the exposed upper portions, a step of removing the mask, and a second etching step of removing all of the remaining under metal layer, whereby said plating metal layer is formed by substantially same material as that of the exposed upper portions or by a material which can be closely contacted with the exposed upper portions and whereby said under metal layer is formed by a material which can be preferentially removed from the exposed upper portions.
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