Digital signal processor evaluation chip and debug method
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United States of America Patent
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Sep 17, 1996
Issued Date -
N/A
app pub date -
Aug 29, 1994
filing date -
Feb 13, 1991
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A digital signal processor evaluation chip has a sequencer for fetching and decoding instructions, and a processor core for executing the instructions. When the sequencer attempts to fetch an instruction from a preset break address, a register transfer instruction is supplied in place of the program instruction at that address, then clock input to the sequencer is halted. After the processor core has executed the register transfer instruction, clock input to the processor means is also halted, leaving the data transferred by the register transfer instruction available to be read.
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