Pulse generator having controlled delay to control duty cycle
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United States of America Patent
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Sep 24, 1996
Issued Date -
N/A
app pub date -
Sep 15, 1995
filing date -
Feb 10, 1994
priority date (Note) -
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Abstract
Five CMOS inverters are connected in a series ring to form an oscillator. Current to the inverters is controlled to establish gate delays of the inverters and thereby determine a frequency of oscillation of the oscillator. The oscillator is included in a phase locked loop where the gate delay of the inverters is selected by selecting the value of a frequency divider of the phase locked loop. The selected delay is used to form a train of pulses with a desired duty cycle.
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