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Abstract

Data processor with a transparency detection data transfer controller. Transparency register stores transparency data. Source address controller calculates source addresses for recall of data to be transferred. A comparator compares recalled data to stored transparency data and indicates whether data to be transferred is to be written to memory. Destination address controller writes data to be transferred into memory at calculated destination addresses if the comparator indicates data to be transferred is to be written to memory. The recalled data is stored in a source register for comparison. In the preferred embodiment data is not written into memory if it matches the transparency data. The transparency register may store a multiple of the minimum amount of data to be transferred. The data to be transferred is organized into data words having a selected size. This selected size is an integral multiple of a minimum amount of data to be transferred. The comparator includes plural data comparators, where each data comparator compares the minimum amount of data to be transferred with a corresponding part of the transparency data. A multiplexer receives these comparison signals and an indication of the selected data size. The multiplexer provides indications of whether the data to be transferred is to be written to memory equal to the number of times the data words of the selected size fit within the transparency register. The selected data size may be a byte, a halfword, a word (32 bits) and a double word and the transparency register stores 64 bits.

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