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Abstract

A microprocessor clocking system is provided for achieving attenuation of a clock signal sent to a microprocessor during initial activation of a connected power supply. By attenuating the clock signal during initial turn-on of the power supply, the clock input to the microprocessor is prevented from erroneous triggering and improper operation. After a delay period has expired, the clock signal is allowed to input directly to the microprocessor input. The delay period is determined as a time exceeding normal spurious noise conditions found on the power supply during initial activation. The microprocessor clocking system includes a clock conditioning circuit configured between a clock signal output of a core logic unit and the clock signal input to a microprocessor. The clock conditioning circuit utilizes a turn-on circuit and a delay circuit coupled to the power supply voltage. The turn-on circuit and delay circuit are both connected to an attenuator, and the attentuator functions to attenuate the clock signal during initial power supply activation.

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First Claim