High speed product term allocation structure supporting logic iteration after committing device pin locations
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United States of America Patent
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Oct 8, 1996
Grant Date -
N/A
app pub date -
May 26, 1995
filing date -
May 26, 1995
priority date (Note) -
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Abstract
A macrocell for flexibly routing product terms from an AND array to output terminals of a programmable logic device. The macrocell allows a variable number of product terms to be retained by the macrocell, and a variable number of product terms to be exported to a second macrocell. The direction in which the product terms are exported can be controlled. The macrocell further allows a variable number of product terms to be received from a third macrocell and routed either to the output terminal of the first macrocell or to the second macrocell in combination with those product terms exported from the first macrocell. Methods for routing product terms using macrocells within a programmable logic device are also provided.
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