Semiconductor memory device having a sleep mode
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United States of America Patent
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Oct 8, 1996
Grant Date -
N/A
app pub date -
Mar 30, 1995
filing date -
Mar 30, 1995
priority date (Note) -
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Abstract
The present invention provides a computer memory device having a sleep mode characterized by extremely low current consumption and relatively large turn on delay. The invention includes circuitry for disabling current sinking elements internal to said device in response to a sleep signal. In one embodiment, the invention includes circuitry for disconnecting the bit lines and memory cell loads of a nonvolatile static random access memory (nvSRAM) array from a source of power in response to a sleep signal. This embodiment is capable of first transferring the data stored in a volatile portion of the array to a nonvolatile portion of the array before entering sleep mode to prevent loss of the data.
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