Synchronous DRAM performing refresh operation a plurality of times in response to each refresh request command
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Oct 15, 1996
Grant Date -
N/A
app pub date -
Nov 13, 1995
filing date -
Nov 10, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor memory device is disclosed as a synchronous DRAM. This DRAM includes a refresh control circuit 4, 5 responding to a refresh request RF supplied thereto and performing a refresh operation at least twice. In the first refresh operation, one of word lines WL is selected and memory cells 13 associated with the selected word line are refreshed, and thereafter a different one of the word lines WL is selected and memory cells 13 associated therewith are refreshed in the next refresh operation.
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