Data processing system including programming voltage inhibitor for an electrically erasable reprogrammable nonvolatile memory
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United States of America Patent
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Oct 15, 1996
Issued Date -
N/A
app pub date -
Oct 24, 1994
filing date -
Dec 20, 1988
priority date (Note) -
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Abstract
A data processing system is provided which includes at least one processing unit and at least one nonvolatile memory which is electrically erasable and reprogrammable at least under the partial control of the processing unit, with the system further including a reinitialization request signal detector which is operatively connected to a programming voltage inhibitor which is capable of inhibiting or preventing the application of at least one signal (V.sub.pp, WE, EE) to the nonvolatile memory, the signal being necessary for the programming of the nonvolatile memory, the reinitialization request signal detector operating to control the inhibitor such that the signal is inhibited from being applied to the nonvolatile memory at least when the reinitialization request signal is detected at a level sufficient to activate reinitialization.
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