Method and apparatus for adaptive memory access
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United States of America Patent
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Oct 15, 1996
Grant Date -
N/A
app pub date -
Jun 30, 1994
filing date -
Jun 30, 1994
priority date (Note) -
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Abstract
A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.
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