Process for aligning etch masks on an integrated circuit surface using electromagnetic energy
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United States of America Patent
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Oct 22, 1996
Grant Date -
N/A
app pub date -
Sep 14, 1994
filing date -
Sep 14, 1994
priority date (Note) -
Expired
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Abstract
Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
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