Importance

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Abstract

A latch circuit comprises, as a circuit corresponding to 1 bit, a flip-flop 50 which is composed of a plurality of NAND gates 11a, 11b, and holds a given signal value and outputs the positive logic value to a Q signal line 5a and the negative logic value to a /Q signal line 5b, and a differential amplifying circuit composed of a plurality of P-type FETs and N-type FETs and having a characteristics such that, an input voltage to the flip-flop 50, when the signal to be held is given, starts to fall before the time point when a drop in voltage of either an X signal line 4a or a /X signal line 4b becomes larger than the difference between a source voltage and a threshold voltage of the NAND gates 11a, 11b. The latch circuit is mainly used as internal elements of a data processor, whereby when the signal is inputted, an voltage of the input signal to the flip-flop 50 of the latch circuit approaches to the threshold voltage of the logic gates constituting the flip-flop 50.

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First Claim