Shadow register file for instruction rollback
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United States of America Patent
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-
Oct 22, 1996
Grant Date -
N/A
app pub date -
Aug 30, 1993
filing date -
Aug 30, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.
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