US Patent No: 5,568,431
Number of patents in Portfolio can not be more than 2000
Memory architecture and devices, systems and methods utilizing the same
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Oct 22, 1996
Issued date -
Sep 21, 1995
filing date -
08/531,755
serial no -
In Force
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Abstract
A memory 200 is provided including a plurality of arrays 202 of memory cells 203. A plurality of registers 211 are also provided, each register 211 for exchanging parallel bits of data with a corresponding one of the arrays 202. Data transfer circuitry 210, 213 is included for transferring parallel bits of data from any selected one of the arrays 202 through the corresponding register 211 to any other selected one of the arrays 202 through the corresponding register 211.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 4,987,559 Semiconductor memory device having a plurality of access ports | 40 | 1989 | |
| 5,463,591 Dual port memory having a plurality of memory cell arrays for a high-speed operation | 39 | 1994 | |
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| 5,161,221 Multi-memory bank system for receiving continuous serial data stream and monitoring same to control bank switching without interrupting continuous data flow rate | 27 | 1988 | |
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| 5,473,566 Memory architecture and devices, systems and methods utilizing the same | 69 | 1994 | |
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| 5,200,925 Serial access semiconductor memory device and operating method therefor | 63 | 1991 | |
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| 5,377,154 Multiple serial-access memory | 15 | 1993 | |
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| 5,270,973 Video random access memory having a split register and a multiplexer | 9 | 1990 | |