Importance

Loading Importance Indicators...

Abstract

An external wearable processor (WP) of a cochlear stimulating system transmits a data signal to an implanted cochlear stimulator (ICS). The ICS is controlled through the data signal so that cochlear stimulation is provided by the ICS only after a determination is made that the WP is in proper signal contact therewith, and that the ICS is functioning properly. The ICS extracts a raw power signal from the data signal and generates different operating voltages from the extracted raw power signal. A detector generates a power bad signal whenever one of the operating voltages is less than a reference voltage. The ICS also detects and generates a carrier detect signal when the data signal is being received. Clock signals are generated within the ICS, and a phase locked loop (PLL) lock signal is generated when the clock signals are phase locked to the data signal. ICS circuitry further checks the parity of the incoming data signal and generates a parity alarm signal whenever a parity error is detected. A back telemetry carrier signal is transmitted from the ICS only when a prescribed combination of the carrier detect, PLL lock, power bad, and parity alarm signals exist. The back telemetry carrier signal, when received at the WP, is used as a handshake signal to signal the WP that the ICS is in proper signal communication with the WP, and that operation of the ICS can proceed.

Loading the Abstract Image...

First Claim