Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
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United States of America Patent
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Nov 5, 1996
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app pub date -
May 20, 1994
filing date -
Apr 6, 1990
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Abstract
An automatic logic-model generation system operates on a behavioral description of an electronic design (e.g., a circuit, a system, etc.) to automatically generate a low-level (i.e., circuit-level) design of the electronic design, to lay out the electronic design for production in the form of an integrated circuit, and to produce logic-level models incorporating accurate timing (and delay) information. A verification process is also performed whereby the logic-level model is automatically verified for accuracy.
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