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Abstract

The present invention relates to a video RAM as a dual port memory, and more particularly to the video RAM which is adjustable to a high speed system clock and a serial data output method thereof. In accordance with the present invention, the video RAM having a data register which outputs a serial data in response to the input of the serial address which is synchronized with a serial clock, comprises a first data I/O line for transferring the data which is synchronized with the even serial address and then is outputted from the data register, and a second data I/O line for transferring the data which is synchronized with the odd serial address and then is outputted from the data register. The video RAM according to the present invention has independent serial data output paths respectively for even address and odd address, thus enabling the serial data to be outputted every period of the serial clock. Consequently, it is possible to reduce the operation cycle time of the video RAM and to transfer data to a CRT at a high speed. In addition, it is possible to reduce the time interval between respective periods of the system clock.

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First Claim