PID loop filter for timing recovery in a sampled amplitude read channel
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United States of America Patent
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Nov 5, 1996
Grant Date -
N/A
app pub date -
Nov 17, 1994
filing date -
Nov 17, 1994
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Abstract
A PID filter employed in a timing recovery phase-locked loop (PLL) for synchronizing the sampling of a read signal from a magnetic read head in a sampled amplitude read channel for magnetic recording. In addition to a proportional and integral term, the PID filter comprises a derivative term to decrease the settling time of the PLL by increasing the phase margin and damping. Consequently, the PLL locks onto the acquisition preamble in a shorter period thereby reducing the necessary preamble length and maximizing storage area for user data. The derivative term of the loop filter is disabled during tracking mode in order to attenuate noise in the phase error and to reduce gain variance associated with tracking arbitrary user data. The structure of the PID loop filter is transformed into an alternative structure in order to minimize the computation path latency between delay registers to avoid limiting the speed of the read channel. To defeat possible harmonic lock conditions caused by non-linearities in the phase-locked loop, a frequency error is added to the accumulation path (integrating path) of the PID filter. A further transformation provides better range and resolution for the PID filter coefficients.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| CIRRUS LOGIC INC | 800 WEST 6TH STREET AUSTIN TX 78701 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Beherns, Richard T | Louisville, CO | 2 | 81 |
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