Bus snoop method and apparatus for computer system having CPU with cache and main memory unit
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United States of America Patent
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Nov 5, 1996
Grant Date -
N/A
app pub date -
Apr 19, 1994
filing date -
Apr 23, 1993
priority date (Note) -
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Abstract
Bus snoop method and apparatus for use in a computer system in which a CPU with cache is coupled to a main memory control unit for controlling a main memory unit through a bus snoop control unit, wherein when the CPU with cache occupies a bus at the time that an external bus master transfers data to the main memory unit, a transfer address for transfer of the data undergoes buffering in the bus snoop control unit and after the CPU with cache ends the execution of an instruction and opens a bus right, the bus snoop control unit transfers the data transfer address subject to buffering to the CPU with cache and a corresponding address recorded in the cache is canceled.
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