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Abstract

A microprocessor includes a clock control system for varying its internal processor clock frequency. The clock control system includes a delay chain composed of delay elements. A set of tap points are distributed at the outputs of selected delay elements. Each tap point is coupled to a respective input line of a latch unit. During operation, an external clock generator provides a clock signal to an input of the delay chain. As a particular rising or falling edge of the clock signal propagates through the delay chain, corresponding signal transitions sequentially appear at the tap points. The latch unit stores the signals in response to a subsequent rising or falling edge of the external clock signal. Thus, an output of the latch unit is indicative of a delay associated with the microprocessor. A decoding circuit may be provided to decode the output of the latch unit and to provide an input to a clock switching circuit which controls the frequency of an internal clock signal. If a high propagation delay exists, the frequency of the internal clock is decreased. If a low propagation delay exists, the frequency is increased.

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First Claim