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Abstract

A computer system has a central processing unit and a functional memory coupled to the central processing unit's memory access circuitry. The functional memory includes random access memory circuitry connected in parallel with field programmable gate array circuitry. The field programmable gate array circuitry receives configuration data from the central processing unit. The configuration data defines what memory addresses the field programmable gate array circuitry will be responsive to and what computational functions the field programmable gate array circuitry will perform. The field programmable gate array circuitry includes input registers for storing data received from the central processing unit when the central processing unit's memory access circuitry asserts a first set of memory addresses defined by the configuration data and result output circuitry for communicating the results computed by the field programmable gate array circuitry. The result output circuitry outputs result data to the central processing unit when the central processing unit's memory access circuitry asserts a second set of memory addresses defined by the configuration data. The functional memory includes access circuitry for routing data signals from the central processing unit to both the random access memory circuitry and the field programmable gate array circuitry in parallel, and for routing data signals from both the random access memory circuitry and the field programmable gate array circuitry to the central processing unit. The field programmable gate array circuitry can be reprogrammed to support different computations for different programs.

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