Fast edge triggered self-resetting CMOS receiver with parallel L1/L2 (master/slave) latch
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United States of America Patent
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Nov 19, 1996
Issued Date -
N/A
app pub date -
Jun 2, 1995
filing date -
Jun 10, 1994
priority date (Note) -
Expired
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Abstract
A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/complement generator circuit (TCG) for generating a data and its complement from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.
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