Method and apparatus for configurable build-in self-repairing of ASIC memories design
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 19, 1996
Grant Date -
N/A
app pub date -
Dec 28, 1994
filing date -
Dec 28, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A logic circuit and a technique for repairing faulty memory cells internally by employing on-chip testing and repairing circuits in an ASIC system. The test circuit detects column line faults, row faults, and data retention faults in a memory array. The repair circuit redirects the original address locations of the faulty memory lines to the mapped address locations of the redundant column or row lines. This repair scheme includes redundant column lines attached to each of the I/O arrays in the memory array and redundant row lines to replace detected memory faults. These testing and repairing procedures are performed within the chip without the aid of any external equipment.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully