Method and apparatus for preforming memory segment limit violation checks
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United States of America Patent
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Nov 19, 1996
Grant Date -
N/A
app pub date -
May 2, 1994
filing date -
May 2, 1994
priority date (Note) -
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Abstract
A method and apparatus for determining if an effective address for a memory access in a computer processor is above an expand-down memory segment. The apparatus comprises a memory segment limit comparison circuit. The segment limit comparison circuit tests every memory access to determine if the memory access reaches above the top limit of an expand-down memory segment. The comparison circuit consists of an adder that adds an effective address of the memory access to an access.sub.-- size value. The access.sub.-- size value consists of the size of the memory access to be performed minus one in the low order bits and a series of '1' bits in the high order bits necessary to generate a carry if the memory access reaches above the top limit of the expand-down memory segment.
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