Apparatus and method for computer processing using an enhanced Harvard architecture utilizing dual memory buses and the arbitration for data/instruction fetch
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United States of America Patent
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Nov 19, 1996
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N/A
app pub date -
Aug 10, 1994
filing date -
Aug 10, 1994
priority date (Note) -
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Abstract
This arbitration unit includes a request controller and two bus controllers. The request controller monitors the instruction fetch or data requests and causes the two bus controllers to implement an instruction fetch or data transfer through one of the two memory interfaces based upon a preassigned priority. Based upon at least one address bit or a control bit contained on a memory management translation table, the request controller identifies which of the memory interfaces to utilize to fetch or transfer data. Preferably, one of the storage areas is random-access memory and the other is read-only memory containing program instructions and read-only data.
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