Importance

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Abstract

A synchronization mechanism for synchronizing an outside clock with a delayed inside clock is provided. The delayed inside clock is distributed across a network of clock lines within the integrated circuit to deskew the clock signal at the supply points. Although the inside clock signal is deskewed, it is nevertheless delayed compared to an input clock signal provided by a pad of the integrated circuit. A distribution line provided on the periphery of the integrated circuit supplies an outside clock signal that is not substantially delayed compared to the input clock signal at the IC's pad. The synchronization mechanism provides synchronization between the outside clock, as received by an input/output block, and the inside clock. The synchronization is required because configurable logic blocks (CLBs) of the IC are typically referenced by the delayed inside clock. The IC can offer significantly reduced chip hold time on input data by referencing the outside clock while supplying data internally using the inside clock reference.

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First Claim