Importance

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Abstract

A serial data receiver includes a clock recovery circuit, a data latch, and a selectable clock inversion mechanism coupled between the clock recovery circuit and the data latch. In one embodiment, the selectable clock inversion mechanism includes an XNOR gate. If a high signal is provided to the XNOR gate, the XNOR gate provides the signal on a recovered clock line to the data latch, thereby placing the window boundaries coincident with, or very near, the rising edges of the input data pulses. The variable phase between these signals is then adjusted for the maximum coincidence of data pulses with the window boundaries. Then, a low signal is provided to the XNOR gate, thereby providing the true signal on the recovered clock line to the data latch. Assuming the symmetry of the recovered clock is truly 50/50, the window moves by exactly 180 degrees. In this manner, the data bits' mean position falls precisely in center of the window, thereby providing substantially ideal window symmetry with minimal phase adjustment and significantly reduced calibration time.

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First Claim