Dynamic clock mode switch
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United States of America Patent
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-
Nov 26, 1996
Issued Date -
N/A
app pub date -
Jul 26, 1995
filing date -
Oct 12, 1993
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A dynamic clock mode switch (11) is provided for switching clock frequencies while allowing continuing operation of a depending system. The switch includes an enable circuit for transmitting an enable signal, a phase-locked loop circuit (PLL) (15) for locking onto an input clock frequency in response to said enable circuit, a PLL lock indicator for receiving a PLL lock signal (29) from said PLL, and a clock multiplexer with a multiplier for multiplying said input clock frequency by a predetermined factor in response to said enable circuit and PLL clock signals.
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