Importance

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Abstract

A low-power data processor in which memory access for reading out an instruction module to be repeatedly executed is controlled to decrease the power consumption of the data processor. The data processor comprises an instruction buffer formed of, for example, a CMOS device operable with low power consumption, the instruction buffer storing the instruction module to be repeatedly executed and being accessed in lieu of an instruction memory, and a repeat control circuit controlling storage of the instruction module in the instruction buffer, so that part of the instruction module ranging from the foremost instruction of the instruction module and corresponding to the capacity of the instruction buffer is stored in the instruction buffer, thereby decreasing the corresponding amount of power consumed for access. The repeat control circuit includes a stacking area so that, even when the instruction module has a multi nested loop structure, that part of the instruction module can be held in the instruction buffer together with the information informing the stored address of the instruction module so as to deal with the instruction module of the multi nested loop structure.

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First Claim