US Patent No: 5,580,831

Number of patents in Portfolio can not be more than 2000

Sawcut method of forming alignment marks on two faces of a substrate

Stats

ATTORNEY / AGENT: (SPONSORED)
 

Importance

Loading Importance Indicators... loading....

Abstract

The present invention is a method for producing alignment marks on opposite faces of a generally flat substrate such as a semiconductor wafer. First, reference cuts are produced at the edges of the substrate at four points around the wafer. Next, the center line is determined on the first face of the substrate between two oppositely disposed reference cuts. First and second grooves are then cut in the first face of the substrate a first predetermined distance from the first center line. Third and fourth grooves are cut in the first face perpendicular to and through the first and second grooves at the first predetermined distance from the second reference cut forming crosshair alignment patterns. Next, the center line is determined on the second face of the substrate between the third and fourth reference cuts, and fifth and sixth grooves are cut in the second face of the substrate a second predetermined distance from the second center line. Finally, seventh and eighth grooves are cut in the second face of the substrate perpendicular to and through the fifth and sixth grooves at the second predetermined distance from the second reference cut. Thus, pairs of crosshairs are located on opposite faces of the substrate based upon reference cuts easily locatable from either side. In a preferred embodiment, the first and second predetermined distances are different from one another, to allow the cuts on opposite faces to be offset to prevent mechanical failure.

Loading the Abstract Image... loading....

First Claim

Related Publications

Loading Related Publications... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
FUJITSU LIMITEDKAWASAKI21511

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Roman, James J Los Altos, CA 21 643

Cited Art

Patent Info (Count) # Cites Year
 
XEROX CORPORATION (3)
4,814,296 Method of fabricating image sensor dies for use in assembling arrays 54 1987
4,822,755 Method of fabricating large area semiconductor arrays 45 1988
5,128,282 Process for separating image sensor dies and the like from a wafer that minimizes silicon waste 42 1991
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
4,534,804 Laser process for forming identically positioned alignment marks on the opposite sides of a semiconductor wafer 31 1984
5,284,792 Full-wafer processing of laser diodes with cleaved facets 20 1993
 
TEXAS INSTRUMENTS INCORPORATED (2)
5,196,378 Method of fabricating an integrated circuit having active regions near a die edge 25 1991
5,393,706 Integrated partial sawing process 26 1993
 
COMMISSARIAT A L'ENERGIE ATOMIQUE (1)
5,174,188 Process and device for marking and cleaving plaquettes of monocrystalline semiconductor materials 12 1990
 
GTE COMMUNICATION SYSTEMS CORPORATION (1)
4,914,829 Image alignment indicators 3 1988
 
HITACHI, LTD. (1)
5,279,992 Method of producing a wafer having a curved notch 7 1992
 
INTEL CORPORATION (1)
4,900,283 Method for arranging chips each having an array of semiconductor light emitting elements 11 1987
 
KABUSHIKI KAISHA TOSHIBA (1)
5,182,233 Compound semiconductor pellet, and method for dicing compound semiconductor wafer 25 1991
 
MITSUBISHI DENKI KABUSHIKI KAISHA (1)
5,302,554 Method for producing semiconductor device 22 1992
 
MOTOROLA, INC. (1)
4,371,598 Method for fabricating aligned patterns on the opposed surfaces of a transparent substrate 7 1981
 
NIKON CORPORATION (1)
4,423,959 Positioning apparatus 32 1983
 
NIPPON ELECTRIC CO., LTD. (1)
4,356,223 Semiconductor device having a registration mark for use in an exposure technique for micro-fine working 24 1981
 
OKI SEMICONDUCTOR CO., LTD. (1)
5,128,280 Fabrication process for wafer alignment marks by using peripheral etching to form grooves 17 1991
 
SVG LITHOGRAPHY, INC., A CORP OF DE (1)
4,547,446 Motion measurement and alignment method and apparatus 12 1983
 
U.S. PHILIPS CORPORATION (1)
4,937,162 Method of obtaining relatively aligned patterns on two opposite surfaces of an opaque slice 5 1988

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (18)
6,250,192 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 12 1996
6,119,675 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 19 1998
6,155,247 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 13 1999
6,006,739 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 33 1999
6,196,096 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 8 1999
6,401,580 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 12 2000
6,255,196 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 4 2000
6,279,563 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 0 2000
6,427,676 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 12 2001
6,631,662 Apparatus for sawing wafers employing multiple indexing techniques for multiple die dimensions 2 2001
6,459,105 Apparatus for sawing wafers employing multiple indexing techniques for multiple die dimensions 3 2001
6,423,616 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 0 2001
6,691,696 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 5 2001
6,578,458 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 9 2002
6,687,990 Sawing method employing multiple indexing techniques and semiconductor device structures fabricated thereby 6 2002
6,897,571 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 0 2002
6,932,077 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions and dicing apparatus 2 2003
7,387,119 Dicing saw with variable indexing capability 0 2005
 
ADVANCED SEMICONDUCTOR ENGINEERING, INC. (1)
7,168,352 Process for sawing substrate strip 1 1999
 
RUBICON TECHNOLOGY, INC. (1)
8,389,099 Asymmetrical wafer configurations and method for creating the same 0 2007
 
TOKYO SEIMITSU CO., LTD. (1)
6,910,403 Method for cutting semiconductor wafer protecting sheet 1 2000
 
XEROX CORPORATION (1)
8,129,258 Method for dicing a semiconductor wafer, a chip diced from a semiconductor wafer, and an array of chips diced from a semiconductor wafer 0 2009
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
6,493,934 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 0 2001