Method and apparatus for managing timing requirement specifications and confirmations and generating timing models and constraints for a VLSI circuit

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United States of America Patent

PATENT NO 5581473
SERIAL NO

08605800

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Abstract

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A repository, a loader, a model generator, a constraint generator, and a number of timing analysis tools, are provided for managing timing requirement specifications and measurements, and generating timing models and constraints of a VLSI circuit. The repository stores the timing specifications and measurements for each pin instances and each flow through arc instances. Timing specifications and measurements are identified by their classes including at least one current specification class and at least one measurement class for one timing analysis tool. Additionally, the repository stores a number of characteristics for each pin instance, the pin compositions of each net, and the hierarchical relationship of the functional block instances. The loader loads the various information into the repository. The timing model generator generates the timing models for the various functional blocks, using the stored information in the repository. The timing constraint generator in cooperation with the timing model generator and at least one timing analysis tool generates the timing constraints for the various functional block instances, using the stored information in the repository, the generated timing models of the functional blocks, and a number of timing analysis scripts.

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Patent Owner(s)

Patent OwnerAddress
SUN MICROSYSTEMS INCCALIFORNIA USA CALIFORNIA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rusu, Stefan Sunnyvale, CA 192 1598
Schulte, Gregory Mountain View, CA 9 111
Taylor, Stuart A Palo Alto, CA 23 1933
Tong, Peter C Mountain View, CA 4 88

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