US Patent No: 5,581,704

Number of patents in Portfolio can not be more than 2000

System for maintaining data coherency in cache memory by periodically broadcasting invalidation reports from server to client

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Abstract

A method and system are provided for maintaining coherency between a server processor and a client processor that has a cache memory. The server may, for example, be a fixed location mobile unit support station. The client may, for example, be a palmtop computer. The server stores a plurality of data values, and the client stores a subset of the plurality of data values in the cache. The server processor periodically broadcasts invalidation reports to the client processor. Each respective invalidation report includes information identifying which, if any, of the plurality of data values have been updated within a predetermined period of time before the server processor broadcasts the respective invalidation report. The client processor determines, based on the invalidation reports, whether a selected data value in the cache memory of the client processor has been updated in the server processor since the selected data value was stored in the cache memory. The client processor invalidates the selected data value in the cache memory of the client processor, if the selected data value has been updated in the server processor.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
PANASONIC CORPORATION OF NORTH AMERICASECAUCUS, NJ302

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Barbara, Daniel Princeton, NJ 10 604
Imielinski, Tomasz Princeton, NJ 21 367

Cited Art

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Patent Citation Ranking

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