Two lane computing systems
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United States of America Patent
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-
Dec 3, 1996
Issued Date -
N/A
app pub date -
Jul 26, 1994
filing date -
Oct 10, 1991
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A dual lane computing system has at least one processor in each lane, each processor having an associated store which stores input data supplied to the processor and their time of arrival. The lanes produce nominally-identical outputs which are supplied to a comparator that detects when there is a discrepancy between the lanes. When a discrepancy is detected, an external processor is loaded with software that simulates the operation of the lanes. The data in the store associated with one of the lane processors is supplied to the simulator processor in respect of the input just prior to the detection of the discrepancy. The simulator simulates the operation of one lane utilizing this data and its output is compared in the comparator with the actual output of that lane as recorded when the discrepancy occurred.
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