Bus structure for multiprocessor system having separated processor section and control/memory section

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5581767
SERIAL NO

08345536

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The processor section comprises a matrix-line layout of processor units; each processor unit combined with adjacent processor units in row and column direction by means of IPC buses, which are two-way buses. The control/memory section comprises arrays of control/memory units corresponding one-to-one to the processor units; each control/memory unit entering instructions and data simultaneously to the corresponding units in the processor section via optical channels to carry out arithmetic operations. By providing grid-like buses on the control/memory-unit arrays, and transferring instructions and data on the buses and sending them to the processor unit corresponding one-to-one to the control/memory unit to which data are transferred via optical channels, the transfer of instructions and data is carried out efficiently between processor units beyond the third closest ones.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
NIPPON SHEET GLASS COMPANY, LIMITEDOSAKA283

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chin, Danny Princeton Junction, NJ 50 1975
Katsuki, Kazuo Hyogo, JP 14 405
Sauer, Donald J Allentown, NJ 39 966

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