Bus structure for multiprocessor system having separated processor section and control/memory section
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United States of America Patent
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-
Dec 3, 1996
Issued Date -
N/A
app pub date -
Nov 28, 1994
filing date -
Jun 16, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The processor section comprises a matrix-line layout of processor units; each processor unit combined with adjacent processor units in row and column direction by means of IPC buses, which are two-way buses. The control/memory section comprises arrays of control/memory units corresponding one-to-one to the processor units; each control/memory unit entering instructions and data simultaneously to the corresponding units in the processor section via optical channels to carry out arithmetic operations. By providing grid-like buses on the control/memory-unit arrays, and transferring instructions and data on the buses and sending them to the processor unit corresponding one-to-one to the control/memory unit to which data are transferred via optical channels, the transfer of instructions and data is carried out efficiently between processor units beyond the third closest ones.
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