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Abstract

A capacitor structure for an integrated circuit and a method of fabrication are described. The capacitor structure is defined by layers forming interconnect metallization and interlayer dielectrics. The latter are relatively thick, and provide high breakdown voltages. Multilevel metallization schemes allow for a stack of a plurality of electrodes to be provided. The electrodes may take the form of stacks of flat plates interconnected in parallel so that the capacitance is the sum of capacitances of alternate layers in the stack. Advantageously each electrode comprises a main portion and a surrounding portion having the form of a protecting ring, coplanar with the main portion of the electrode. The ring prevents thinning of the dielectric near edges of electrode during fabrication, to improve control of breakdown voltages for high voltage applications. Alternative electrode structures employing a plurality of interconnected fingers, and particularly a configuration having interdigitated fingers, are provided to increase the capacitance per unit surface area. Parallel electrode fingers are stacked in vertical alignment, or offset, and interconnected to provide vertical, horizontal or inclined stacks having different patterns of polarities, thereby forming capacitors of various configurations. The capacitor structures have particular application for high voltage (>100 V), low leakage and high frequency (MHz/GHz) applications.

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First Claim